Solid state image pickup device and its driving method

ABSTRACT

IT-CCD has a number of photoelectric conversion elements disposed in a pixel shift layout in a plurality of rows and columns, a plurality of vertical transfer CCDs for transferring signal charges accumulated in the photoelectric conversion elements toward a horizontal transfer CCD in a zigzag way, and readout gate regions for controlling for corresponding photoelectric conversion elements to read the signal charges accumulated in the photoelectric conversion elements to the vertical transfer CCDs. In manufacturing such IT-CCD, for twos of a plurality of photoelectric conversion element columns, a vertical transfer CCD is provided in an area in plan view between the two photoelectric conversion element columns, and a plurality of charge transfer stages constituting a adjusting portion are formed downstream of the downstream ends of the vertical transfer CCDs. The horizontal transfer CCD can be formed easily without using highly sophisticated ultra fine patterning techniques and power consumption of the horizontal transfer CCD can be suppressed low.

This application is based on Japanese Patent Applications HEI 11-273409,filed on Sep. 27, 1999, and 2000-280586, filed on Sep. 14, 2000, theentire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid state image pickup device to beused as an area image sensor and its driving method, and moreparticularly to a solid state image pickup device suitable for use as anarea image sensor of an electronic still camera, and its driving method.

2. Description of the Related Art

After mass production techniques for charge-coupled devices (CCD) havebeen established, video cameras, electronic still cameras and the likeutilizing CCD type solid state image pickup devices as area imagesensors are prevailing rapidly. CCD type solid image pickup devices areclassified into several types, depending upon their structures. One typeis an interline transfer type solid state image pickup device (thissolid state image pickup device is hereinafter described as “IT-CCD” inabbreviation).

IT-CCD has a number of photoelectric conversion elements disposed alonga plurality of columns and rows at a constant pitch. Each photoelectricconversion element column is constituted of a plurality of photoelectricconversion elements, and each photoelectric conversion element row isalso constituted of a plurality of photoelectric conversion elements.

A number of photoelectric conversion elements each made of a p-nphotodiode are formed, for example, by forming a p-type well in adesired principal surface of a semiconductor substrate and formingn-type regions (n-type impurity doped regions) having a desired shape inthe p-type well as many as the number of photoelectric conversionelements to be formed. If necessary, a p⁺-type region (p⁺-type impuritydoped region) is formed on each n-type region. Signal charges areaccumulated in the n-type region. The n-type region functions as asignal charge accumulation region.

In this specification, the term “photoelectric conversion element” isused in some cases to mean only the signal charge accumulation region.In this specification, it is assumed that “adjacent to the photoelectricconversion element” means “adjacent to the signal charge accumulationregion constituting the photoelectric conversion element” and that“contiguous to the photoelectric conversion element” means “contiguousto the signal charge accumulation region constituting the photoelectricconversion element”.

A charge transfer channel is formed adjacent to each photoelectricconversion element column. IT-CCD has a plurality of charge transferchannels. Each charge transfer channel is used for transferring signalcharges accumulated in all photoelectric conversion elements of thephotoelectric conversion element column adjacent to the charge transferchannel.

A plurality of transfer electrodes traversing in plan view each chargetransfer channel are formed on an electric insulating film over thesurface of the semiconductor substrate. A cross area in plan viewbetween each transfer electrode and the charge transfer channelfunctions as one charge transfer stage. A vertical transfer CCD istherefore formed by the channel transfer channel and transferelectrodes.

In this specification, a charge transfer stage forming region of eachtransfer electrode constituting the vertical transfer CCD is called a“transfer path forming area”.

Generally, each vertical transfer CCD of an interlace drive type IT-CCDhas two charge transfer stages per one photoelectric conversion element.Generally, each vertical transfer CCD of an all-pixel read type IT-CCDhas three or four charge transfer stages per one photoelectricconversion element. One IT-CCD has vertical transfer CCDs same in numberas the number of photoelectric conversion element columns formed inIT-CCD.

Each photoelectric conversion element photoelectrically convertsincidence light into signal charges and stores the charges. The signalcharges stored in each photoelectric conversion element are read to thecorresponding charge transfer channel at a predetermined timing.

For a read control of signal charges from the photoelectric conversionelement to the charge transfer channel, a readout gate region is formedadjacent to each photoelectric conversion element on the surface of thesemiconductor substrate. This readout gate region has generally aconductivity type opposite to that of the photoelectric conversionelement and charge transfer channel, in order to form a potentialbarrier relative to the signal charges. Each readout gate region is alsoadjacent to a predetermined region of the charge transfer channel.

A readout gate electrode structure is formed on the readout gate region.The readout gate electrode structure is constituted of a partial regionof the transfer path forming area of a predetermined transfer electrodeconstituting the vertical transfer CCD. As a high voltage is applied tothe readout gate structure to remove the potential barrier in thereadout gate region, signal charges accumulated in the photoelectricconversion element can be read to the charge transfer channel.

Signal charges read to each charge transfer channel are transferred toan output transfer path by each vertical transfer CCD constituted of thecharge transfer channel. The output transfer path is generally made ofCCD (this CCD is called in some cases a “horizontal transfer CCD”).

The output transfer path made of the horizontal transfer CCD has Ncharger transfer stages per one vertical transfer CCD. Each chargetransfer stage has usually one potential barrier and one potential well.In this case, N=2. If the charge transfer stage has a uniform potential,then N=3 or larger.

The output transfer path sequentially transfers the received signalcharges along a lengthwise direction of the photoelectric conversionelement row (this direction is hereinafter simply called a “rowdirection”), to an output unit. Similar to the vertical transfer CCD,the output transfer path is formed on the semiconductor substrate.

The vertical transfer CCD and horizontal transfer CCD have thephotoelectric conversion function similar to photodiodes. In order toavoid unnecessary photoelectric conversion by the vertical transfer CCDand horizontal transfer CCD, a light shielding film is formed on an areafrom a photosensitive area with photoelectric conversion elements to thehorizontal transfer CCD area. The light shielding film has an openingwith a predetermined shape formed on each photoelectric conversionelement (photodiode). An opening is formed for each photoelectricconversion element. Generally, the inner edge of the opening is inner inplan view than the outer edge, in plan view, of the signal chargeaccumulation region of the photoelectric conversion element.

A pixel is constituted of: one photoelectric conversion element; onereadout gate region formed contiguous to the photoelectric conversionelement; one readout gate electrode structure covering in plan view thereadout gate region; and two to four charge transfer stages (two to fourcharge transfer stages on the vertical transfer CCD) associating to thephotoelectric conversion element. The area of the photoelectricconversion element exposed in plan view in the opening functions as alight receiving area.

The shape and area of the light receiving area of the pixel of IT-CCDare therefore substantially determined by the shape and area, in planview, of the opening formed in the light shielding film.

The performance such as a resolution and sensitivity of IT-CCD widelyprevailing nowadays is desired to be improved further.

The resolution of IT-CCD depends largely on the pixel density. Thehigher the pixel density, the resolution is easier to be improved. Thesensitivity of IT-CCD depends largely on the area of the light receivingarea of each pixel. The larger the light receiving area of each pixel,the sensitivity is easier to be raised.

IT-CCD described in Japanese Patent Publication No. 2825702 (althoughthis Publication has the title “Solid State Image Pickup Device”, inthis specification it is described as “IT-CCD”) has an improved pixeldensity while the reduction in the light receiving area of each pixel issuppressed.

This IT-CCD has a number of photoelectric conversion elements disposedalong a plurality of columns and rows at a constant pitch. Eachphotoelectric conversion element column and each photoelectricconversion element row contain a plurality of photoelectric conversionelements. A plurality of photoelectric conversion elements constitutingan even column are shifted in the column direction by about a half ofthe pitch between adjacent photoelectric conversion elements in eachcolumn, from a plurality of photoelectric conversion elementsconstituting an odd column. Similarly, a plurality of photoelectricconversion elements constituting an even row are shifted in the rowdirection by about a half of the pitch between adjacent photoelectricconversion elements in each row, from a plurality of photoelectricconversion elements constituting an odd row. Each photoelectricconversion element column contains photoelectric conversion elements ofonly the even rows or odd rows.

A vertical transfer CCD is disposed for each photoelectric conversionelement column in order to transfer signal charges accumulated in thephotoelectric conversion elements. The vertical transfer CCD is adjacentto the corresponding photoelectric conversion element column. Eachvertical transfer CCD includes a plurality of transfer electrodes. Thesetransfer electrodes are disposed in a honeycomb shape, in general. Ineach rectangular area defined by a plurality of transfer electrodesdisposed in the honeycomb shape, the photoelectric conversion element isdisposed in plan view.

Each vertical transfer CCD is used for transferring signal chargesaccumulated in all photoelectric conversion elements of thephotoelectric conversion element column adjacent to the verticaltransfer CCD. The vertical transfer CCD transfers the signal charges ina zigzag way to the predetermined destination.

In IT-CCD described in the above-described Publication, a number ofphotoelectric conversion elements and a plurality of transfer electrodes(transfer electrodes for the vertical transfer CCD) are disposed asdescribed above to improve the pixel density while the reduction in thelight receiving area of each pixel is suppressed.

In this specification, the above-described layout of a number ofphotoelectric conversion elements is hereinafter called a “pixel-shiftlayout”.

For example, a ½-inch, two-million-pixel IT-CCD with the pixel-shiftlayout used for an electronic still camera has a pixel pitch of about2.8 μm in a lengthwise direction (this direction is hereinafter called a“direction D_(H)”) of the photoelectric conversion element row. A⅓-inch, two-million-pixel IT-CCD with the pixel-shift layout used for anelectronic still camera has a pixel pitch of about 2.1 μm in thedirection D_(H).

A four-phase drive type CCD is widely used as the vertical transfer CCD,and a two-phase drive type CCD is widely used as the horizontal transferCCD.

Pixels can be formed relatively easily at a pitch of 2.1 μm in thedirection D_(H) for IT-CCD having a four-phase drive type verticaltransfer CCDs and two-phase drive type horizontal CCD. However, thehorizontal transfer CCD of this IT-CCD has four electrodes per onevertical transfer CCD. Namely, four transfer electrodes are formed in anarea having a width of 2.1 μm. The width of each transfer electrode isabout 0.5 μm.

In forming IT-CCD having such a horizontal transfer CCD, highlysophisticated ultra fine patterning techniques are required to make thechip size compact.

Since the horizontal transfer CCD has four transfer electrodes per onevertical transfer CCD, pulse supply terminals for supplying drive pulsesto the horizontal transfer CCD have large electrostatic capacitance.

In order to raise the read frame frequency of a high resolution IT-CCDhaving pixels larger than two million pixels, high speed drive pulses atabout 200 MHz are used for driving the horizontal transfer CCD.

Therefore, a power consumption of the horizontal transfer CCD increases,for example, to several tens mW. An increase in the power consumptionresults in a short battery life of a battery driven electronic stillcamera.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an IT-CCD and itsdriving method capable of improving a pixel density with ease withoutrelying upon highly sophisticated ultra fine patterning techniques andsuppressing an increase in a power consumption with ease.

According to one aspect of the present invention, there is provided asolid state image pickup device, comprising: a semiconductor substrate;a number of photoelectric conversion elements disposed on a surface ofthe semiconductor substrate in a plurality of columns and rows, aphotoelectric conversion element column and a photoelectric conversionelement row each being composed of a plurality of photoelectricconversion elements, a plurality of photoelectric conversion elements ofan even column being shifted in a column direction by about a half ofthe pitch between adjacent photoelectric conversion elements in eachphotoelectric conversion element column, from a plurality ofphotoelectric conversion elements of an odd column, and a plurality ofphotoelectric conversion elements of an even row being shifted in a rowdirection by about a half of the pitch between adjacent photoelectricconversion elements in each photoelectric conversion element row, from aplurality of photoelectric conversion elements of an odd row; chargetransfer channels each provided for two photoelectric conversion elementcolumns and formed in the surface of the semiconductor substrate in anarea in plan view between the two photoelectric conversion elementcolumns, said charge transfer channel extending as a whole along adirection of the photoelectric conversion element column and having azigzag shape; a plurality of transfer electrodes formed on thesemiconductor substrate, traversing in plan view each of said chargetransfer channels, said transfer electrode having transfer path formingareas same in number as said charge transfer channels, the transfer pathforming area forming one charge transfer stage in a cross area in planview with a corresponding charge transfer channel, adjacent two transferelectrodes with one photoelectric conversion element row beinginterposed therebetween repeating in plan view divergence andconvergence and surrounding in plan view each photoelectric conversionelement in the photoelectric conversion element row of an even or oddrow to define photoelectric conversion element region, said transferelectrode extending as a whole along a direction of the photoelectricconversion element row; a readout gate region provided for eachphotoelectric conversion element in the surface of the semiconductorsubstrate to be contiguous to the photoelectric conversion element andto a corresponding charge transfer channel, said readout gate regioncorresponding to the photoelectric conversion element of the even rowand said readout gate region corresponding to the photoelectricconversion element of the odd row being covered in plan view withdifferent transfer electrodes; and an adjusting portion formeddownstream of downstream ends of said charge transfer channels, saidadjusting portion including a plurality of charge transfer stages foradjusting a phase of signal charges transferred from each of said chargetransfer channels.

According to another aspect of the present invention, there is provideda driving method for a solid state image pickup device comprising: asemiconductor substrate; a number of photoelectric conversion elementsdisposed on a surface of the semiconductor substrate in a plurality ofcolumns and rows, a photoelectric conversion element column and aphotoelectric conversion element row each being composed of a pluralityof photoelectric conversion elements, a plurality of photoelectricconversion elements of an even column being shifted in a columndirection by about a half of the pitch between adjacent photoelectricconversion elements in each photoelectric conversion element column,from a plurality of photoelectric conversion elements of an odd column,and a plurality of photoelectric conversion elements of an even rowbeing shifted in a row direction by about a half of the pitch betweenadjacent photoelectric conversion elements in each photoelectricconversion element row, from a plurality of photoelectric conversionelements of an odd row; charge transfer channels each provided for twophotoelectric conversion element columns and formed in the surface ofthe semiconductor substrate in an area in plan view between the twophotoelectric conversion element columns, said charge transfer channelextending as a whole along a direction of the photoelectric conversionelement column and having a zigzag shape; a plurality of transferelectrodes formed on the semiconductor substrate, traversing in planview each of said charge transfer channels, said transfer electrodehaving transfer path forming areas same in number as said chargetransfer channels, the transfer path forming area forming one chargetransfer stage in a cross area in plan view with a corresponding chargetransfer channel, adjacent two transfer electrodes with onephotoelectric conversion element row being interposed therebetweenrepeating in plan view divergence and convergence and surrounding inplan view each photoelectric conversion element in the photoelectricconversion element row of an even or odd row to define photoelectricconversion element region, said transfer electrode extending as a wholealong a direction of the photoelectric conversion element row; a readoutgate region provided for each photoelectric conversion element in thesurface of the semiconductor substrate to be contiguous to thephotoelectric conversion element and to a corresponding charge transferchannel, said readout gate region corresponding to the photoelectricconversion element of the even row and said readout gate regioncorresponding to the photoelectric conversion element of the odd rowbeing covered in plan view with different transfer electrodes; and anadjusting portion formed downstream of downstream ends of said chargetransfer channels, said adjusting portion including a plurality ofcharge transfer stages for adjusting a phase of signal chargestransferred from each of said charge transfer channels, the drivingmethod comprising the steps of: reading the signal charges accumulatedin each photoelectric conversion element of at least one photoelectricconversion element row, to the charge transfer channel corresponding tothe photoelectric conversion element via the readout gate regioncontiguous to the photoelectric conversion element, during one verticalblanking period; and converting the signal charges read to the chargetransfer channel into an image signal and outputting the image signal,during a period after the one vertical blanking period and before a nextvertical blanking period.

In the solid state image pickup device described above, one verticaltransfer CCD is constituted of one charge transfer channel and aplurality of transfer electrodes traversing in plan view the chargetransfer channels. In other words, one vertical transfer CCD is providedfor two photoelectric conversion element columns. Although only onevertical transfer CCD is provided for two photoelectric conversionelement columns, signal charges can be read from all photoelectricconversion elements.

With this solid state image pickup device, the number of verticaltransfer CCDs necessary for reading signal charges from allphotoelectric conversion elements can be reduced to a half of the numberof vertical transfer CCDs of a conventional solid state image pickupdevice. The total number of charger transfer stages of the horizontaltransfer CCD and the total number of transfer electrodes can thereforebe reduced to halves of those of a conventional solid state image pickupdevice.

For example, a solid image pickup device having a large number of pixelsof two millions can be manufactured without narrowing the width of atransfer electrode of each transfer stage of the horizontal transferCCD. Namely, without using highly sophisticated ultra fine patterningtechniques, a solid image pickup device having a large number of pixelsof two millions can be manufactured.

Since the total number of charge transfer stages of the horizontaltransfer CCD can be reduced to a half of that of a conventional solidstate image pickup device, an increase in the electrostatic capacitanceof pulse supply terminals used for supplying drive pulses to thehorizontal transfer CCD can be suppressed. An increase in powerconsumption can therefore be suppressed easily.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view showing an IT-CCD according to a firstembodiment.

FIG. 2 is an enlarged plan view partially showing a photosensitive areaof IT-CCD shown in FIG. 1.

FIG. 3 is a schematic plan view showing one charge transfer channel 31shown in FIG. 2.

FIG. 4 is a schematic plan view showing one transfer electrode 32 shownin FIG. 2.

FIG. 5 is a schematic plan view showing one transfer electrode 33 shownin FIG. 2.

FIG. 6A is a schematic cross sectional view taken along line A—A shownin FIG. 2, and FIG. 6B is a schematic cross sectional view taken alongline B—B shown in FIG. 2.

FIG. 7 is a schematic cross sectional view showing an example of ahorizontal transfer CCD of IT-CCD of the first embodiment.

FIG. 8 is a diagram showing a connection between IT-CCD shown in FIG. 1and drive pulse supplying means used for interlace driving of IT-CCD.

FIGS. 9A and 9B are schematic cross sectional views partially showingIT-CCD according to a second embodiment.

FIG. 10 is a plan view showing an example of a color filter array ofIT-CCD of the second embodiment.

FIG. 11 is a schematic cross sectional view partially showing ahorizontal transfer CCD of IT-CCD of the second embodiment.

FIG. 12 is a schematic plan view showing IT-CCD according to a thirdembodiment.

FIG. 13 is a schematic plan view showing IT-CCD according to a fourthembodiment.

FIG. 14 is a schematic cross sectional view partially showing an outputtransfer path being composed of a three-layer polysilicon type CCD ofIT-CCD according to a fifth embodiment.

FIGS. 15A, 15B and 15C are diagrams illustrating directions of shiftingmicro lenses.

FIGS. 16A, 16B, 16C, 16D and 16E are plan views showing examples of acolor filter array of a complementary color type.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a schematic plan view of an IT-CCD 100 according to a firstembodiment. This IT-CCD is of an interlace drive type having a number ofpixels disposed in the pixel-shift layout.

In this simplified example shown in FIG. 1, thirty-two photoelectricconversion elements 22 are disposed in 8 rows×8 columns in thepixel-shift layout. A photoelectric conversion element column 20 in theodd column contains photoelectric conversion elements 22 of only the oddrows, and a photoelectric conversion element column 20 in the evencolumn contains photoelectric conversion elements 22 of only the evenrows.

In an actual IT-CCD, the number of pixels are several hundred thousandsto several millions. Even in this case, the pixel-shift layout is usedso that the photoelectric conversion element column 20 in the odd columncontains photoelectric conversion elements 22 of only the odd rows andthe photoelectric conversion element column 20 in the even columncontains photoelectric conversion elements 22 of only the even rows. Ifthe leftmost first photoelectric conversion element column 20 isomitted, the photoelectric conversion element column 20 of the oddcolumn contains the photoelectric conversion elements 20 of only theeven rows, and the photoelectric conversion element column 20 of theeven column contains the photoelectric conversion elements 20 of onlythe odd rows.

IT-CCD shown in FIG. 1 has: a photosensitive area 10 defined on thesurface area of a semiconductor substrate; an adjustment portion 60formed outside of the photosensitive area 10; an output transfer path 70formed outside of the adjusting portion 60; and an output unit 80continuously formed at one end of the output transfer path 70.

Formed on the surface of the semiconductor substrate 1 in thephotosensitive area 10 are eight photoelectric conversion elementcolumns 20, eight photoelectric conversion element rows 21, fourvertical transfer CCDs 30 and thirty two readout gate regions 40.

Each photoelectric conversion element column 20 is constituted of fourphotoelectric conversion elements 22 made of the n-type region in thep-type well, and each photoelectric conversion element row 21 is alsoconstituted of four photoelectric conversion elements 22.

Each vertical transfer CCD 30 has one charge transfer channel (not shownin FIG. 1) made of the n-type region in the p-type well formed in thesurface of the semiconductor substrate 1, five transfer electrodes 32formed on an electric insulating film over the semiconductor substrate 1and traversing in plan view the charge transfer channels, and fourtransfer electrodes 33 formed on the electric insulating film over thesemiconductor substrate 1 and traversing in plan view the chargetransfer channels. For example, the transfer electrodes 32 are made of afirst polysilicon layer, and the transfer electrodes 33 are made of asecond polysilicon layer. These transfer electrodes 32 and 33 are formedalternatively along the charge transfer channel.

Each readout gate region 40 is contiguous to both the correspondingphotoelectric conversion element 22 and the corresponding area of thecharge transfer channel constituting the vertical transfer CCD 30corresponding to the photoelectric conversion element 22. In FIG. 1,each of the readout gate regions 40 is hatched for easy visualdiscrimination.

The adjusting portion 60 has twelve charge transfer stages connected toone ends (downstream ends) of the charge transfer channels constitutingthe vertical transfer CCDs 30. Each charge transfer stage is constitutedof an adjusting charge transfer channel (not shown) continuous with thecharge transfer channel and one of three transfer electrodes 61, 62 and63 formed on the semiconductor substrate 1 and traversing in plan viewthe adjusting charge transfer channel. The charge transfer stage isformed at each crossing area between each adjusting charge transferchannel and each transfer electrode 61, 62, 63.

The transfer electrode 61 has a transfer path forming area 61T at eachcrossing area in plan view with each adjusting charge transfer channel.These transfer path forming areas 61T are connected together byconnection areas 61C. The transfer electrode 62 has a transfer pathforming area 62T at each crossing area in plan view with each adjustingcharge transfer channel. These transfer path forming areas 62T areconnected together by connection areas 62C. The transfer electrode 63has a transfer path forming area 63T at each crossing area in plan viewwith each adjusting charge transfer channel. These transfer path formingareas 63T are connected together by connection areas 63C. As will belater described, each of the transfer electrodes 32 and 33 in thephotosensitive area 10 has a similar structure to that of the transferelectrode 61, 62, or 63.

Each adjusting charge transfer channel extends along a directiontraversing the transfer electrodes 61, 62, 63 in plan view at thetransfer path forming areas 61T, 62T, 63T.

The transfer electrode 32, 33 and the transfer electrodes 61, 62 and 63are drawn in FIG. 1 spaced apart from each other so as to facilitatevisual discrimination therebetween. However, in actual, the transferelectrode 32 nearest to the adjusting portion 60 and the transferelectrode 61 are partially overlapped at least at the boundary thereof.The transfer electrodes 32 and 33, and the transfer electrodes 61 and62, 62 and 63 are similarly overlapped. These transfer electrodes areelectrically insulated from each other by electric insulating films.

The adjusting portion 60 includes the charge transfer stage foradjusting the charge transfer direction from that of the verticaltransfer CCD 30 to the photoelectric conversion element columndirection. In the example shown in FIG. 1, the charge transfer stageconstituted of the transfer path forming area 61T corresponds to such anadjusting charge transfer stage.

The output transfer path 70 receives signal charges supplied from eachvertical transfer CCD 30 via the adjusting portion 60, and sequentiallytransfers the signal charges to the output unit 80 along the lengthwisedirection of the photoelectric conversion element row 21.

The output unit 80 converts the signal charges supplied from the outputtransfer path 70 into a voltage signal by using a floating capacitor(not shown). The signal charges after detection (conversion) are drainedin a power source (not shown) via an unrepresented reset transistor.

Four pulse supply terminals 85 a, 85 b, 85 c and 85 d are disposedoutside of the photosensitive area 10 in order to supply predetermineddrive pulses to the transfer electrodes 32 and 33 and transferelectrodes 61, 62, and 63.

Each of the pulse supply terminals 85 a, 85 b, 85 c, and 85 d iselectrically connected to every fourth electrode among the transferelectrodes 32, 33, 61, 62 and 63. Four-phase drive pulses are suppliedfrom the pulse supply terminals 85 a, 85 b, 85 c, and 85 d to thetransfer electrodes 32, 33, 61, 62 and 63.

Two pulse supply terminals 88 a and 88 b are disposed outside of thephotosensitive area 10 to supply predetermined drive pulses to theoutput transfer path 70.

Reference numeral 51 shown in FIG. 1 represents an opening formedthrough a light shielding film 50 to be later described.

The structure of the light shielding area 10 will be described withreference to FIGS. 2, 3, 4, 5, 6A and 6B, by taking as an example then-type silicon semiconductor substrate 1 with the p-type well. Theinvention is not limited only to this structure.

FIG. 2 is an enlarged plan view partially showing the photosensitivearea 10 shown in FIG. 1, and FIG. 3 is a schematic plan view of a chargetransfer channel 31 shown in FIG. 2. FIG. 4 is a schematic plan view ofa transfer electrode 32, and FIG. 5 is a schematic plan view of atransfer electrode 33. FIG. 6A is a schematic cross sectional view takenalong line A—A shown in FIG. 2, and FIG. 6B is a schematic crosssectional view taken along line B—B shown in FIG. 2.

As shown in FIG. 2, in each photoelectric conversion element column 20in the photosensitive area 10, a predetermined number of photoelectricconversion elements 22 (signal charge accumulation regions) are formedto be aligned in a predetermined direction D_(v) (indicated by an arrowin FIG. 2) at a constant pitch P₁. In each photoelectric conversionelement row 21, a predetermined number of photoelectric conversionelements 22 (signal charge accumulation regions) are formed to bealigned in a predetermined direction D_(H) (indicated by an arrow inFIG. 2) at a constant pitch P₂.

A plurality of photoelectric conversion elements 22 (signal chargeaccumulation regions) constituting an even column 20 are shifted in thecolumn direction (direction D_(v)) by about a half of the pitch P₁, fromthe photoelectric conversion elements 22 constituting an odd column 20(refer to FIG. 2). Similarly, a plurality of photoelectric conversionelements 22 (signal charge accumulation regions) constituting an evenrow 21 are shifted in the row direction (direction D_(H)) by about ahalf of the pitch P₂, from the photoelectric conversion elements 22constituting an odd column 20 (refer to FIG. 2).

In this specification, “about a half of the pitch P₁” is intended toinclude not only a value P₁/2 but also those values different from butnear P₁/2, the difference being ascribed to manufacture errors, rounderrors of a pixel position resulted from design or mask manufacture, orother errors, as far as they can be considered substantially equivalentto P₁/2 in terms of the IT-CCD performance and its image quality. Thisis also applied to “about a half of the pitch P₂” in this specification.

The shape of each photoelectric conversion element 22 is substantiallyhexagonal in plan view, the size of each photoelectric conversionelement 22 are substantially the same in plan view.

One charge transfer channel 31 is provided for two photoelectricconversion element columns 20, and formed in a surface of thesemiconductor substrate 1 between the two photoelectric conversionelement columns 20.

As shown in FIGS. 2 and 3, each charge transfer channel 31 has aplurality of sections lying in a line. Each section has a directiondifferent from that of the next section such that the charge transferchannel 31 shows a zigzag shape with the sections being continuous alongthe direction D_(v) as a whole. R₁, R₂. . . R₆ in FIG. 3 represent thesections of the charge transfer channel 31.

Two kinds of transfer electrodes 32 and 33 are formed traversing eachcharge transfer channel 31 (refer to FIG. 2).

As shown in FIG. 4, each transfer electrode 32 has a predeterminednumber of transfer path forming areas 32T and a predetermined number ofconnection areas 32C having a width narrower than that of the transferpath forming area 32T. The total number of transfer path forming areas32T of the transfer electrode 32 is the same as that of charge transferchannels 31 formed in the photosensitive area 10. The connection area32C is constituted of a first connection area 32C₁, a second connectionarea 32C₂ and a third connection area 32C₃. The first and thirdconnection areas 32C, and 32C₃ extend in the direction D_(H). The secondconnection area 32C₂ obliquely extends from one end of the firstconnection area 32C, to one end of the third connection area 32C₃ andhas an obtuse angle θ₁ relative to the first and third connection areas32C₁, and 32C₃.

A transfer path forming area 32T is continuous with the left end (leftend in FIGS. 2 and 4) of a first connection area 32C₁, and has an obtuseangle θ₂ relative to the first connection area 32C₁. The transfer pathforming area 32T is continuous with the right end (right end in FIGS. 2and 4) of a third connection area 32C₃ of another connection area 32 andhas the obtuse angle θ₂ relative to the third connection area 32C₃.

As shown in Fig. 2, each transfer path forming area 32T covers in planview one section of the charge transfer channel 31. The transfer pathforming area and section constitute one charge transfer stage. Eachtransfer path forming area 32T also covers in plan view a readout gateregion 40. A partial region of the transfer path forming area 32T coversin plan view the readout gate region 40 constitutes a readout gateelectrode structure 32G (refer to FIG. 4) for reading signal chargesfrom the photoelectric conversion element 22.

As shown in FIG. 5, each transfer electrode 33 has a predeterminednumber of transfer path forming areas 33T and a predetermined number ofconnection areas 33C having a width narrower than that of the transferpath forming area 33T. The total number of transfer path forming areas33T of the transfer electrode 33 is the same as that of charge transferchannels 31 formed in the photosensitive area 10. The connection area33C is constituted of a first connection area 33C₁, a second connectionarea 33C₂ and a third connection area 33C₃. The first and thirdconnection areas 33C₁ and 33C₃ extend in the direction D_(H). The secondconnection area 33C₂ obliquely extends from one end of the firstconnection area 33C₁ to one end of the third connection area 33C₃ andhas an obtuse angle θ₃ relative to the first and third connection areas33C₁ and 33C₃.

A transfer path forming area 33T is continuous with the left end (leftend in FIGS. 2 and 4) of a first connection area 33C₁ of a connectionarea 33C and has an obtuse angle θ₄ relative to the first connectionarea 33C₁. The transfer path forming area 33T is continuous with theright end (right end in FIGS. 2 and 4) of a third connection area 33C₃of another connection area 33C and has the obtuse angle θ₄ relative tothe third connection area 33C₃.

As shown in FIG. 2, each transfer path forming area 33T covers in planview one section of the charge transfer channel 31. The transfer pathforming area and section constitute one charge transfer stage. Eachtransfer path forming area 33T also covers in plan view a readout gateregion 40. A partial region of the transfer path forming area 33Tcovering the readout gate region 40 constitutes a readout gate electrodestructure 33G (refer to FIG. 4) for reading signal charges from thephotoelectric conversion element.

One vertical transfer CCD 30 (refer to FIG. 2) is composed of the chargetransfer stages constituted of the transfer path forming areas 32T andthe charge transfer stages constituted of the transfer path formingareas 33T connected alternately. Each charge transfer stage of thevertical transfer CCD 30 has a different direction from that of the nextcharge transfer stage, and the charge transfer stages extend as a wholealong the direction D_(v) (refer to FIG. 2). The vertical transfer CCD30 transfers in the direction D_(v) signal charges accumulated in thephotoelectric conversion elements 22 constituting two photoelectricconversion element columns 20 disposed on both sides of the verticaltransfer CCD 30.

Adjacent two transfer electrodes 32 and 33 overlap at the connectionareas 32C₁ and 33C₁ or connection areas 32C₃ and 33C₃ when they traversethe photoelectric conversion element column 20. When they traverse thenext photoelectric conversion element column 20, they separate andsurround the photoelectric conversion element 22 constituting the nextphotoelectric conversion element column 20. The adjacent two transferelectrodes 32 and 33 extend along the direction D_(H) as a whole byrepeating the above described overlap and separation (refer to FIG. 2).

In the structure shown in FIG. 1, an upper transfer electrode 32 and alower adjacent transfer electrodes 33 surround in plan view thephotoelectric conversion elements 22 in an odd row. An upper transferelectrode 33 and lower transfer electrodes 32 surround in plan view thephotoelectric conversion elements 22 in an even row.

The adjacent two transfer electrodes 32 and 33 surround onephotoelectric conversion element 22 in isolated state and define onephotoelectric conversion element region having a hexagonal shape. Theshapes, sizes and directions of these photoelectric conversion elementareas are substantially the same. Namely, the transfer electrodes 32 and33 form a honeycomb shape (refer to FIG. 2).

The “hexagonal shape” used in this specification is intended to mean ahexagon (including a regular hexagon) with all internal angles having anobtuse angle, defined by an area surrounded by the adjacent two transferelectrodes 32 and 33. The hexagon includes a shape having roundedcorners of a hexagon, a heptagon obtained by shifting one side of ahexagon to inner or outer side thereof and linking the side withadjacent two sides, an octagon obtained by shifting two sides of ahexagon to inner or outer side thereof and linking the sides withadjacent sides, or a shape having rounded corners of the heptagon oroctagon. Each photoelectric conversion element 22 is positioned in planview in the photoelectric conversion element region having the“hexagonal shape”.

Each photoelectric conversion element region in the photoelectricconversion element column 20 in the odd columns as counted from theleftmost column in FIG. 1 is defined in plan view by one connection area32C and the next right transfer path forming area 32T and by oneconnection area 33C and the next right transfer path forming area 33T.

Each photoelectric conversion element region in the photoelectricconversion element column 20 in the even columns as counted from theleftmost column in FIG. 1 is defined in plan view by one transfer pathforming area 32T and the next right connection area 32C and by onetransfer path forming area 33T and the next right connection area 33C.

The transfer electrodes 32 and 33 are drawn separated in FIG. 1 tofacilitate visual discrimination therebetween. However, in practice,these transfer electrodes 32 and 33 are overlapped at the connectionareas 32C₁ and 33C₁, at the connection areas 32C₃ and 33C₃ and at thetransfer path forming areas 32T and 33T.

Each photoelectric conversion element 22 constituting the photoelectricconversion element column 20 at the right end in the photosensitive area10 (right end in FIG. 1) may not be surrounded by the adjacent twotransfer electrodes 32 and 33. Namely, the right end connection areas32C and 33C necessary for surrounding in plan view each photoelectricconversion element 22 constituting the right end photoelectricconversion element column 20 may be omitted (refer to FIG. 1). This isalso applicable to each photoelectric conversion element 22 constitutingthe left end photoelectric conversion element column 20 in thephotosensitive area 10.

As shown in FIGS. 6A and 6B, the photoelectric conversion element 22 isa buried type photodiode constituted of a predetermined region of ap-type well 2 formed in one principal surface of a semiconductorsubstrate 1, an n-type region 3 formed in the predetermined region ofthe p-type well 2, and a burying p⁺-type layer 4. The n-type region 3functions as the signal charge accumulation region.

An electric insulating film (silicon oxide film) 5 is formed on thep⁺-type layer 4. The electric insulating film (silicon oxide film) 5covers not only the p⁺-type layer 4 but also a surface of thesemiconductor substrate 1. The material of the electric insulating film5 may be a silicon oxide film, a two-layer film of a silicon oxide filmand a silicon nitride film, a three-layer film of a silicon oxide film,a silicon nitride film and a silicon oxide film, or the like.

Adjacent two photoelectric conversion elements 22 along the directionD_(v) are separated, for example, by a channel stop region 25 made of ap⁺-type layer (refer FIG. 6A).

The charge transfer channel 31 is formed, for example, by forming ann-type region in a predetermined area of the p-type well 2 formed in theprincipal surface of the semiconductor substrate 1. The charge transferchannel 31 and photoelectric conversion element 22 are separated, forexample, by a channel stop region 35 made of the p⁺-type layer,excepting the area where the readout gate region 40 is formed (refer toFIG. 6B).

The transfer electrode 32 is made of a polysilicon layer formed on anelectric insulating film (silicon oxide film) 5 on the semiconductorsubstrate 1. Each transfer electrode 32 is covered with an electricinsulating layer 34 such as a silicon oxide film. The transfer electrode33 is also made of a polysilicon layer. Each transfer electrode 33 iscovered with an electric insulating layer such as a silicon oxide film,if necessary.

Each readout gate region 40 (refer to FIG. 6B) is formed of apredetermined area of the p-type well 2 formed in the principal surfaceof the semiconductor substrate 1. Readout gate electrode structures 32Gand 33G are formed on the electric insulating film (silicon oxide film)5 on the readout gate regions 40 (refer to FIG. 2).

An electric insulating film (passivation film) 74 coves an exposedsurface of the electric insulating film 5, an exposed surface of theelectric insulating layer 34 and transfer electrodes 33. A lightshielding film 50 to be later described is formed on the electricinsulating film (passivation film) 74. The electric insulating film 74covers the transfer electrodes 32 and 33 and electrically insulates theelectrodes 32 and 33 from the light shielding film 50. The material ofthe electric insulating film 74 may be a silicon oxide film, a two-layerfilm of a silicon oxide film and a silicon nitride film, a three-layerfilm of a silicon oxide film, a silicon nitride film and a silicon oxidefilm, or the like.

Reference numeral 51 in FIGS. 1, 2, 6A and 6B represents the openingformed through the light shielding film 50.

In IT-CCD 100 having the above-described photosensitive area 10, onepixel includes: (a) one photoelectric conversion element 22; (b) twocharge transfer stages formed adjacent to the photoelectric conversionelement 22, the charge transfer stages including the charge transferstage constituted of the transfer path forming area 32T and the chargetransfer stage constituted of the transfer path forming area 33T; and(c) one readout gate region 40 formed between the photoelectricconversion element 22 and the charge transfer stage constituted of thecharge transfer forming area 32T or 33T.

As described earlier, an area from the photosensitive area 10 to theoutput transfer path 70 of IT-CCD is covered in plan view with the lightshielding film 50 to prevent unnecessary photoelectric conversion by thevertical transfer CCDs 30.

As shown in FIGS. 6A and 6B, the light shielding film 50 has an opening51 of a predetermined shape on each photoelectric conversion element 22in the photosensitive area 10. One opening 51 is formed for onephotoelectric conversion element 22. The inner edge of the opening 51 isinner in plan view than the outer edge, in plan view, of the signalcharge accumulation region (n-type region 3) of the photoelectricconversion element 22. The area of the photoelectric conversion element22 exposed in plan view in the opening 51 functions as a light receivingarea of each pixel (this light receiving area is hereinafter called insome cases “light receiving area 51”).

The material of the light shielding film 50 is a metal thin film made ofaluminum, chromium, tungsten, titan and molybdenum, an alloy thin filmmade of two metals of these metals, a multi-layer metal thin film madeof a combination of the metal thin films or a combination of the metalthin film and the alloy thin film, or the like.

The opening (light receiving area) 51 has a pentagonal shape in planview. The shapes, sizes and directions of these openings (lightreceiving areas) 51 are substantially the same.

Light incident upon the photoelectric conversion element 22 via theopening (photosensitive area) 51 is photoelectrically converted by thephotoelectric conversion element 22 into signal charges. The signalcharge is read from the n-type region 3 as the signal chargeaccumulation area of the photoelectric conversion element 22, to thevertical transfer CCD 30 via the readout gate region 40 being contiguousto the photoelectric conversion element 22. In this case, apredetermined field shift pulse is applied to the transfer electrode 32(readout gate electrode structure 32G) or transfer electrode 33 (readoutgate electrode structure 33G).

The signal charges read to the vertical transfer CCD 30 are sequentiallytransferred in the charge transfer stages of the vertical transfer CCD30 and reach the output transfer path 70 via the adjusting portion 60(refer to FIG. 1).

FIG. 7 is a schematic cross sectional view showing an example of theoutput transfer path 70. The output transfer path 70 shown in FIG. 7 iscomposed of a two-phase drive type CCD having a two-layer polysiliconelectrode structure. In FIG. 7, constituent element similar to thoseshown in FIG. 6A or FIG. 6B are represented by using identical referencenumerals, and the description thereof is omitted.

An output transfer path (horizontal transfer CCD) 70 shown in FIG. 7 hasa charge transfer channel 71 formed in the surface of a semiconductorsubstrate 1, a plurality of transfer electrodes 72 and 73 formed on anelectric insulating film (silicon oxide film) 5 on the semiconductorsubstrate 1, an electric insulating film (passivation film) 74 formed onthe transfer electrodes 72 and 73 and a light shielding film 50 formedon the electric insulating film (passivation film) 74.

The charge transfer channel 71 is formed by alternately forming apredetermined number of n⁺-type regions 71 a and n-type regions 71 b inpredetermined areas of a p-type well 2 formed in the principal surfaceof the semiconductor substrate 1. The n⁺-type region 71 a containsn-type impurities at a high concentration, and the n-type region 71 bcontains n-type impurities at a low concentration. The charge transferchannel 71 extends along the direction D_(H).

Each transfer electrode 72 is made of a polysilicon layer. A siliconoxide film 75 covers the surface of the transfer electrode 72. Thetransfer electrode 72 is formed over the n⁺-type region 71 a. Eachtransfer electrode 73 is also made of a polysilicon layer. The transferelectrode 73 is formed over the n-type region 71 b.

The transfer electrodes 72 and 73 traverse the charge transfer channel71. The end portions of the transfer electrode 73 on the transferelectrode 72 side overlap the transfer electrodes 72. The transferelectrodes 72 and 73 have a so-called overlapping transfer electrodestructure.

A potential well region is formed by the n⁺-type region 71 a and thetransfer electrode 72 formed on the electric insulating film (siliconoxide film) 5 over the n⁺-type region 71 a. Similarly, a potentialbarrier region is formed by the n-type region 71 b and the transferelectrode 73 formed on the electric insulating film (silicon oxide film)5 over the n-type region 71 b.

Both the transfer electrode 73 forming the potential barrier region andthe transfer electrode 72 forming the potential well region on the nextdownstream side are applied with a predetermined voltage level at thesame time to form one charge transfer stage.

In the output transfer path 70, two charge transfer stages are providedfor one vertical transfer CCD 30. Therefore, the vertical transfer CCDs30 are connected via the adjusting portion 60 to every two chargetransfer stages of the output transfer path 70.

The signal charges transferred from the vertical transfer CCD 30 via theadjusting portion 60 are received by the output transfer path 70 in thepotential well region thereof.

An electric insulating film 74 covers the transfer electrodes 72 and 73and electrically insulates the transfer electrodes 72 and 73 from thelight shielding film 50. The material of the electric insulating film 74may be a silicon oxide film, a two-layer film of a silicon oxide filmand a silicon nitride film, a three-layer film of a silicon oxide film,a silicon nitride film and a silicon oxide film, or the like.

The light shielding film 50 prevents light from entering the outputtransfer path 70 and the like to avoid unnecessary photoelectricconversion by the output transfer path 70 and the like.

The signal charges sequentially transferred in the output transfer path70 eventually reach the output unit 80 (refer to FIG. 1) whereat thesignal charges are converted into a voltage signal and amplified. Theamplified voltage signal is output to a predetermined circuit.

In IT-CCD 100 described above, one vertical CCD 30 is provided for twophotoelectric conversion element columns 20. Although only one verticalCCD 30 is provided for two photoelectric conversion element columns 20,signal charges can be read from all photoelectric conversion elements 22of IT-CCD 100.

The number of vertical transfer CCDs of IT-CCD 100 necessary for readingsignal charges from all photoelectric conversion elements 22 is a halfof those of a conventional IT-CCD. The total number of charge transferstages in the output transfer path (horizontal transfer CCD) 70 cantherefore be reduced to a half of those of a conventional IT-CCD.

As a result, an IT-CCD with a large number of pixels, for example, 2million pixels, can be manufactured without narrowing the widths oftransfer electrodes of each charge transfer stage of the output transferpath 70.

In a ⅓-inch, two-million-pixel IT-CCD with the pixel-shift layout, apitch of photoelectric conversion element columns 20 in thephotosensitive area 10 is about 2 μm as described earlier. However, inIT-CCD 100 of the first embodiment, a pitch of vertical transfer CCDs 30in the photosensitive area 10 is about 4 μm. Four transfer electrodesare formed in the region about 4 μm width of the output transfer path(horizontal transfer CCD) 70. The width of each of the transferelectrodes 72 and 73 of the output transfer path 70 can therefore be setas wide as about 1 μm.

An IT-CCD with a large number of pixels, for example, 2 million pixels,can therefore be manufactured without utilizing highly sophisticatedultra fine patterning techniques.

The total number of charge transfer stages of the output transfer path70 can be reduced to a half of that of a conventional IT-CCD. Anincrease in the electrostatic capacitance of the pulse supply terminals88 a and 88 b (refer to FIG. 1) to be used for supplying drive pulses tothe output transfer path 70 can therefore be suppressed. An increase inthe consumption power can be easily suppressed.

The shapes, sizes and directions of the photosensitive areas 51 ofIT-CCD 100 are substantially the same. A light convergence efficiencyand sensitivity of a pixel is not likely to have a difference betweenadjacent two photoelectric conversion element rows of IT-CCD 100.

In order to drive IT-CCD 100, a drive pulse supply means is used forsupplying predetermined drive pulses to the transfer electrodes 32 and33, transfer electrodes 61, 62 and 63 and output transfer path 70.

An example of a driving method will be described by taking as an examplean interlace drive method for IT-CCD 100. In this example, the interlacedrive method is performed by dividing one frame into four fieldsincluding first to fourth fields.

As shown in FIG. 8, a drive pulse supply means 105 for interlace-drivingIT-CCD 100 includes, for example, a sync signal generator 101, a timinggenerator 102, a vertical drive circuit 103 and a horizontal drivecircuit 104.

The sync signal generator 101 generates various pulses necessary forsignal processing, such as a vertical sync pulse and a horizontal syncpulse. The timing generator 102 generates timing signals used forgenerating a four-phase vertical pulse signals necessary for driving thevertical transfer CCDs 30, field shift pulses necessary for readingsignal charges from the photoelectric conversion elements 22, atwo-phase horizontal pulse signals necessary for driving the outputtransfer path 70, and other pulses.

The vertical drive circuit 103 generates vertical pulse signals inresponse to the timing signals, and applies each vertical pulse signalto the transfer electrodes 32, 33, 61 62 or 63 via the pulse supplyterminals 85 a, 85 b, 85 c, or 85 d. The horizontal drive circuit 104generates horizontal pulse signals in response to the timing signals andapplies each horizontal pulse signal to the output transfer path 70 viathe pulse supply terminals 88 a or 88 b.

A vertical pulse signal applied to the pulse supply terminal 85 a isrepresented by V_(a), a vertical pulse signal applied to the pulsesupply terminal 85 b is represented by V_(b), a vertical pulse signalapplied to the pulse supply terminal 85 c is represented by V_(c), and avertical pulse signal applied to the pulse supply terminal 85 d isrepresented by V_(d). A horizontal pulse signal applied to the pulsesupply terminal 88 a is represented by Ha, and a horizontal pulse signalapplied to the pulse supply terminal 88 b is represented by H_(b). Thephase of the horizontal pulse signal H_(a) is shifted by 180° from thatof the horizontal pulse signal H_(b).

At a proper timing during a first vertical blanking period defined by ablanking pulse, a low level vertical pulse V_(L) is applied to the pulsesupply terminals 85 a and 85 b and a high level vertical pulse V_(H) isapplied to the pulse supply terminals 85 c and 85 d. While thesevertical pulses V_(L) and V_(H) are applied, a higher level field shiftpulse V_(R) is applied to the pulse supply terminal 85 d. Uponapplication of the field shift pulse V_(R), signal charges accumulatedin the photoelectric conversion elements 22 of the first and fifth pixelrows constituting the first field are read to the vertical transfer CCDs30 (signal charge read process).

The “pixel row” means a group of pixels serially disposed in the rowdirection, and the pixel rows are called a first pixel row, a secondpixel row, . . . , an n-th pixel row (n is a positive integer), startingfrom the row nearest to the output transfer path 70 (this is alsoapplicable to IT-CCDs of other embodiments). One pixel row includes onephotoelectric conversion element row 21 (refer to FIG. 1). IT-CCD 100has eight pixel rows, the first to eighth pixel rows.

After the field shift pulse V_(R) is applied, vertical pulse signalshaving a predetermined waveform V_(a), V_(b), V_(c) and V_(d) areapplied to the pulse supply terminals 85 a, 85 b, 85 c and 85 d. Thesignal charges read to the vertical transfer CCDs 30 are thereforesequentially transferred toward the output transfer path 70.

The signal charges read from the photoelectric conversion elements 22 ofthe first pixel row are transferred to the output transfer path 70during a first horizontal blanking period following the verticalblanking period. These signal charges are sequentially output from theoutput unit 80 during a first effective signal period following thefirst horizontal blanking period (image signal output process).

The signal charges read from the photoelectric conversion elements 22 ofthe fifth pixel row are transferred to the output transfer path 70during a second horizontal blanking period following the first effectivesignal period. These signal charges are sequentially output from theoutput unit 80 during a second effective signal period following thesecond horizontal blanking period (image signal output process).

At a proper timing during a second vertical blanking period defined bythe blanking pulse after the second effective signal period, the lowlevel vertical pulse V_(L) is applied to the pulse supply terminals 85 aand 85 b and the high level vertical pulse V_(H) is applied to the pulsesupply terminals 85 c and 85 d. While these vertical pulses V_(L) andV_(H) are applied, the field shift pulse V_(R) is applied to the pulsesupply terminal 85 c. Upon application of the field shift pulse V_(R),signal charges accumulated in the photoelectric conversion elements 22of the second and sixth pixel rows constituting the second field areread to the vertical transfer CCDs 30 (signal charge read process).

The signal charges read from the photoelectric conversion elements 22 ofthe second pixel row are transferred to the output transfer path 70during a third horizontal blanking period following the second verticalblanking period. These signal charges are sequentially output from theoutput unit 80 during a third effective signal period following thethird horizontal blanking period (image signal output process).

The signal charges read from the photoelectric conversion elements 22 ofthe sixth pixel row are transferred to the output transfer path 70during a fourth horizontal blanking period following the third effectivesignal period. These signal charges are sequentially output from theoutput unit 80 during a fourth effective signal period following thefourth horizontal blanking period (image signal output process).

At a proper timing during a third vertical blanking period defined bythe blanking pulse after the fourth effective signal period, the highlevel vertical pulse V_(H) is applied to the pulse supply terminals 85 aand 85 b and the low level vertical pulse V_(L) is applied to the pulsesupply terminals 85 c and 85 d. While these vertical pulses V_(H) andV_(L) are applied, the field shift pulse V_(R) is applied to the pulsesupply terminal 85 b. Upon application of the field shift pulse V_(R),signal charges accumulated in the photoelectric conversion elements 22of the third and seventh pixel rows constituting the third field areread to the vertical transfer CCDs 30 (signal charge read process).

The signal charges read from the photoelectric conversion elements 22 ofthe third pixel row are transferred to the output transfer path 70during a fifth horizontal blanking period following the third verticalblanking period. These signal charges are sequentially output from theoutput unit 80 during a fifth effective signal period following thefifth horizontal blanking period (image signal output process).

The signal charges read from the photoelectric conversion elements 22 ofthe seventh pixel row are transferred to the output transfer path 70during a sixth horizontal blanking period following the fifth effectivesignal period. These signal charges are sequentially output from theoutput unit 80 during a sixth effective signal period following thesixth horizontal blanking period (image signal output process).

At a proper timing during a fourth vertical blanking period defined bythe blanking pulse after the sixth effective signal period, the highlevel vertical pulse V_(H) is applied to the pulse supply terminals 85 aand 85 b and the low level vertical pulse V_(L) is applied to the pulsesupply terminals 85 c and 85 d. While these vertical pulses V_(H) andV_(L) are applied, the field shift pulse V_(R) is applied to the pulsesupply terminal 85 a. Upon application of the field shift pulse V_(R),signal charges accumulated in the photoelectric conversion elements 22of the fourth and eighth pixel rows constituting the fourth field areread to the vertical transfer CCDs 30 (signal charge read process).

The signal charges read from the photoelectric conversion elements 22 ofthe fourth pixel row are transferred to the output transfer path 70during a seventh horizontal blanking period following the fourthvertical blanking period. These signal charges are sequentially outputfrom the output unit 80 during a seventh effective signal periodfollowing the seventh horizontal blanking period (image signal outputprocess).

The signal charges read from the photoelectric conversion elements 22 ofthe eighth pixel row are transferred to the output transfer path 70during an eighth horizontal blanking period following the seventheffective signal period. These signal charges are sequentially outputfrom the output unit 80 during an eighth effective signal periodfollowing the eighth horizontal blanking period (image signal outputprocess).

The above operations executed during the period from the first verticalblanking period to the eighth effective signal period are repeated tosequentially output interlaced image output signals, image outputsignals of respective fields, from the output unit 80.

A color IT-CCD can be obtained by forming a color filter array on IT-CCD100. A camera requiring a color image signal for each field executes acoloring signal process for each field image output signal output fromthe output unit 80 to obtain a color image signal of each field.

A camera requiring a color image signal for a frame temporarily storesconsecutive four field image output signals in a frame memory, andexecutes a coloring signal process for the image output signals of oneframe to obtain a color image signal for each frame. In this case, it ispreferable to use a mechanical shutter in order to prevent the exposedtiming of each field from being shifted. The mechanical shutter isclosed after the end of the first vertical blanking period until thestart of the fourth vertical blanking period so as not to enter anoptical image in pixels. In this manner, the first to fourth field imageoutput signals at the same timing can be obtained. This is applicablealso to a camera requiring a black-white image signal of one frame. Fora camera requiring only one frame image, the mechanical shutter isclosed after the first vertical blanking period. It is thereforepossible to suppress the generation of smear in the first to fourthfield images.

A camera requiring color image signals for respective interlaced fieldstemporarily stores image output signals of a predetermined number offields necessary for obtaining the color image signal through additiveor subtractive color processes in a field memory, and executes acoloring signal process for the image output signal stored in the fieldmemory to obtain a color image signal. In this case, one frame isdivided into, for example, two fields.

If a camera requiring a color image signal of each interlaced field isrealized by using IT-CCD 100 of the first embodiment, for example, thefirst and second fields may form a new field and the third and fourthfields may form another new field. A predetermined color filter array isformed on IT-CCD 100 in order to obtain a color image from image outputsignals of the first and second fields and from image output signals ofthe third and fourth fields.

It is preferable to use a mechanical shutter in order to prevent a shiftof the exposed timing between two fields constituting one field used forobtaining a color image signal or between two fields constituting oneframe. For example, the mechanical shutter is closed after the end ofthe first vertical blanking period until the start of the secondvertical blanking period, and after the end of the third verticalblanking period until the start of the forth vertical blanking period,so as not to enter an optical image in pixels. In this manner, the fieldimages (color images) at the same timing can be obtained.

IT-CCD 100 of the first embodiment has a simpler structure than IT-CCDpractically used; micro lenses are provided to raise the photoelectricconversion efficiency of photoelectric conversion elements 22, and acolor filter array is provided for color IT-CCD.

In forming micro lenses, a planarized film is formed on thephotosensitive area 10. The planarized film is used also as a focusadjusting layer. For black-white IT-CCD, a micro lens array having apredetermined number of micro lenses is formed on the planarized film,and for color IT-CCD, a color filter array is formed on the planarizedfilm and a second planarized film is formed on the color filter array toform a micro lens array on the second planarized film. For bothwhite-black and color IT-CCDs, each micro lens covers in plan view thelight receiving area of the pixel.

FIGS. 9A and 9B are cross sectional views partially showing IT-CCD 110according to a second embodiment. FIGS. 9A and 9B partially show thephotosensitive area of IT-CCD 110. IT-CCD 110 has a color filter arrayand a micro lens array added to the structure of IT-CCD 100 of the firstembodiment. IT-CCD 110 is a color IT-CCD.

In FIGS. 9A and 9B, like constituent elements to those shown in FIGS. 6Aand 6B are represented by using identical reference numerals, and thedescription thereof is omitted.

A first planarized film 90 is disposed on the light shielding film 50formed on the electric insulating film (passivation film) 74 and on thelight receiving area 51 of each pixel. A color filter array 91 is formedon the surface of the first planarized film 90. A second planarized film92 is formed on the color filter array 91. A micro lens array having apredetermined number of micro lenses 93 is formed on the surface of thesecond planarized film 92.

The first planarized film 90 is formed, for example, by coatingtransparent resin such as photoresist to a desired thickness by a spincoating method.

The color filter array 91 has, for example, red filters 91R, greenfilters 91G and blue filters 91B formed in a predetermined pattern. Forexample, the color filter array 91 is formed by depositing a resin(color resin) pattern including desired pigment or dye byphotolithography or the like.

As described with IT-CCD 100 of the first embodiment, transferelectrodes 32 and 33 are formed in a honeycomb shape. Each photoelectricconversion element 22 is positioned in plan view in a photoelectricconversion element region of a hexagonal shape or a substantiallyhexagonal shape defined by adjacent two transfer electrodes 32 and 33 atevery second photoelectric conversion element column. The red filters91R, green filters 91G and blue filters 91B of the color filter array 91are disposed in a tortoise shell pattern.

The layout of color filters of the color filter array 91 is set so thatfull color information can be obtained through additive or subtractivecolor processes by using signal charges stored in photoelectricconversion elements of predetermined two pixel rows, e.g., adjacent twopixel rows, of IT-CCD having the color filter array 91.

FIG. 10 is a partial plan view showing an example of the color filterarray 91. Vertical transfer CCDs 30 are also drawn in FIG. 10. In thiscolor filter array 91 shown in FIG. 10, a color filter column made ofonly green filters 91G and a color filter column made of alternatelydisposed blue filters 91B and red filters 91R are alternately disposed.Each vertical transfer CCD 30 is positioned under the border linebetween the color filter column made of only green filters 91G and thenext right color filter column or color filter column made ofalternately disposed blue filters 91B and red filters 91R, and extendsin a zigzag way like the border line.

Each of the color filters 91R, 91G and 91B covers in plan view the lightreceiving area 51 of each pixel. Alphabets R, G and B of color filtersshown in FIG. 10 represent colors of the color filters.

The second planarized film 92 shown in FIGS. 9A and 9B is formed, forexample, by coating transparent resin such as photoresist to a desiredthickness by a spin coating method.

Each micro lens 93 shown in FIGS. 9A and 9B covers in plan view thelight receiving area 51 of each pixel. These micro lenses 93 are formed,for example, by forming a transparent resin (e.g., photoresist film)having a refractive index of about 1.3 to 2.0 by photolithography andpartitioning it in a tortoise shell pattern, and thereafter melting eachpartitioned transparent resin pattern by heat treatment to round thecorners, and cooling the pattern.

Similar to IT-CCD 100 of the first embodiment, IT-CCD 110 with the colorfilter array 91 and micro lens array has the output transfer path. Inthe area of the output transfer path, the first planarized film 90 isformed on the light shielding film 50 of the output transfer path 70shown in FIG. 7, and the second planarized film 92 is formed on thefirst planarized film 90.

FIG. 11 is a schematic cross sectional view showing the output transferpath 70 a of IT-CCD 110. In FIG. 11, similar constituent elements tothose shown in FIGS. 7, 9A and 9B are represented by using identicalreference numerals, and the description thereof is omitted.

The first planarized film 90 shown in FIG. 11 is formed at the same timewhen the first planarized film 90 (refer to FIGS. 9A and 9B) is formedon the photosensitive area 10. The second planarized film 92 shown inFIG. 11 is formed at the same time when the second planarized film 92(refer to FIGS. 9A and 9B) is formed on the color filter array 91.

As apparent from the layout of color filters of the color filter array91 of IT-CCD 110 shown in FIG. 10, the green filters 91G are disposed onphotoelectric conversion elements 22 of one of two adjacent pixel rows,and the blue and red color filters 91B and 91R are disposed alternatelyon photoelectric conversion elements 22 of the other pixel row. The blueand red filters 91B and 91R of the other pixel row may be disposedalternately in this order or reversed order.

Full color information is obtained from the signal charges ofphotoelectric conversion elements 22 of the pixel row having only greenfilters 91G and from the signal charges of photoelectric conversionelements 22 of the pixel row having blue and red color filters 91B and91R disposed alternately.

If a light convergence efficiency and sensitivity of a pixel has adifference between adjacent two pixel rows, there is also a differenceof a light convergence efficiency and sensitivity of a pixel between thepixel row having only green filters 91G and the pixel row having blueand red filters 91B and 91R disposed alternately. As a result, signaloutputs obtained from signal charges accumulated in the photoelectricconversion elements of adjacent two pixel rows have a difference betweena ratio of the red signal output to the green signal output and a ratioof the blue signal output to the green signal output. This differenceresults in a color unbalance of output signals of IT-CCD 110. A colorunbalance of output signals results in color shading in a reproducedimage.

The photosensitive area of IT-CCD 110 is the same as the photosensitivearea 10 of IT-CCD 100, and as described earlier the shapes, sizes anddirections of light receiving areas 51 formed in the photosensitive area10 of IT-CCD 100 are substantially the same.

Although the pixel-shift layout is employed in IT-CCD 110, adjacent twopixel rows are not therefore likely to have a difference in the lightconvergence efficiency and sensitivity of a pixel. Color shading is alsonot likely to occur. It is easy to suppress a difference in the lightconvergence efficiency and sensitivity of a pixel.

From the same reason described with IT-CCD 100 of the first embodiment,IT-CCD 110 can easily improve the pixel density without using highlysophisticated ultra fine patterning techniques and can easily suppressan increase in power consumption.

Next, IT-CCD according to a third embodiment will be described withreference to FIG. 12.

FIG. 12 is a schematic plan view of IT-CCD 120 according to the thirdembodiment. IT-CCD 120 has the similar structure to that of IT-CCD 100excepting: (i) the shape of a light receiving area of each pixel; (ii)the number of transfer electrodes constituting the adjusting portion;(iii) the number of pulse supply terminals for supplying predetermineddrive pulses to the transfer electrodes constituting each verticaltransfer CCD and the transfer electrodes in the adjusting portion; and(iv) a specification of interconnection between the pulse supplyterminals and transfer electrodes. In FIG. 12, like constituent elementsto those shown in FIG. 1 are represented by using identical referencenumerals used in FIG. 1, and the description thereof is omitted.

As shown in FIG. 12, the shape of the light receiving area 51 a of eachpixel of IT-CCD 120 is a rhombus having a longer diagonal substantiallyparallel to the direction D_(v) and a shorter diagonal substantiallyparallel to the direction D_(H).

The number of charge transfer stages in the adjusting portion 60 isincreased by two for each vertical transfer CCD 30. The increased chargetransfer stages are formed on the downstream side of the transferelectrode 63. Each increased charge transfer stage transfers signalcharges along the direction D_(v). The increased charge transfer stagesare constituted of a transfer electrode 64 or 65 having the shape sameas that of the transfer electrode 63.

The transfer electrode 64 has four transfer path forming areas 64Textending in the direction D_(v). The four transfer path forming areas64T are connected by connection areas 64C extending in the directionD_(H). The transfer electrode 65 has four transfer path forming areas65T extending in the direction D_(v). The four transfer path formingareas 65T are connected by connection areas 65C extending in thedirection D_(H). In each increased charge transfer stage, an adjustingcharge transfer channel extends in the direction D_(v).

IT-CCD 120 has six pulse supply terminals 85 a, 85 b, 85 c ₁, 85 c ₂, 85d ₁ and 85 d ₂ to supply predetermined drive pulses to the transferelectrodes 32 and 33 and transfer electrodes 61 to 65.

The pulse supply terminals 85 ₁c, and 85 c ₂ are formed by dividing thepulse supply terminal 85 c shown in FIG. 1 into two terminals. The pulsesupply terminals 85 d ₁, and 85 d ₂ are formed by dividing the pulsesupply terminal 85 d shown in FIG. 1 into two terminals.

These pulse supply terminals 85 a, 85 b, 85 c ₁, 85 c ₂, 85 d ₁ and 85 d₂ are electrically connected to predetermined transfer electrodes amongthose electrodes 32, 33, 61, 62, 63,64 and 65.

The shapes, sizes and directions of light receiving areas 51 of pixelsof IT-CCD 120 shown in FIG. 12 are substantially the same. Therefore,from the same reason as that of IT-CCD 100 of the first embodiment,although the pixel-shift layout is employed, adjacent two pixel rows canbe easily prevented from having a difference in the light convergenceefficiency and sensitivity of a pixel.

From the same reason described with IT-CCD 100 of the first embodiment,IT-CCD 120 can easily improve the pixel density without using highlysophisticated ultra fine patterning techniques and can easily suppressan increase in power consumption.

A color IT-CCD can be formed by providing IT-CCD 120 with a color filterarray. The color filter array can be formed, for example, by using aprocess similar to that used for forming the color filter array ofIT-CCD 110 of the second embodiment.

If IT-CCD 120 is modified to a color IT-CCD, from the same reason asthat described with IT-CCD 110 of the first embodiment, color shading isnot likely to occur.

Similar to IT-CCD 100, IT-CCD 120 can be interlace-driven. In theinterlace drive, a vertical pulse signal V_(a) is applied to the pulsesupply terminal 85 a, and a vertical pulse signal V_(b) is applied tothe pulse supply terminal 85 b. A vertical pulse signal Vc is applied tothe pulse supply terminals 85 c ₁ and 85 c ₂, and a vertical pulsesignal V_(d) is applied to the pulse supply terminals 85 d ₁ and 85 d ₂.A horizontal pulse signal Ha is applied to the pulse supply terminal 88a, and a horizontal pulse signal Hb is applied to the pulse supplyterminal 88 b.

Similar to IT-CCD 100 of the first embodiment, one frame is divided intofour fields, first to fourth fields. An image signal output of eachfield can be obtained by an operation similar to that used for IT-CCD100. This operation is executed for the first to fourth fields to obtainan image output signal of one frame.

IT-CCD 120 can be driven by thinning the number of pixel rows from whichsignal charges are read, to a quarter of the total number of pixel rows.During the thinning drive operation, at a proper timing during a firstvertical blanking period defined by a blanking pulse, for example, a lowlevel vertical pulse V_(L) is applied to the pulse supply terminals 85 aand 85 b and a high level vertical pulse V_(H) is applied to the pulsesupply terminals 85 c ₁, 85 c ₂, 85 d ₁ and 85 d ₂. While these verticalpulses V_(L) and V_(H) are applied, a field shift pulse V_(R) is appliedto the pulse supply terminal 85 d ₂.

Upon application of the field shift pulse V_(R), signal chargesaccumulated in the photoelectric conversion elements 22 of the firstpixel row are read to the vertical transfer CCDs 30 (signal charge readprocess).

Next, the vertical pulse signals V_(a), V_(b), V_(c) and V_(d) of oneperiod are applied to each of the pulse supply terminals 85 a, 85 b, 85c ₁, 85 c ₂, 85 d ₁ and 85 d ₂. The signal charges read to the verticaltransfer CCDs are therefore transferred toward the output transfer path70 by an amount corresponding to one charge transfer stage.

Thereafter, the low level vertical pulse V_(L) is applied to the pulsesupply terminals 85 a and 85 b and the high level vertical pulse V_(H)is applied to the pulse supply terminals 85 c ₁, 85 c ₂, 85 d ₁ and 85 d₂. While these vertical pulses V_(L) and V_(H) are applied, the fieldshift pulse V_(R) is applied to the pulse supply terminal 85 c ₂. Uponapplication of the field shift pulse V_(R), signal charges accumulatedin the photoelectric conversion elements 22 of the second pixel row areread to the vertical transfer CCDs 30 (signal charge read process).

The signal charges read from the photoelectric conversion elements 22 ofthe first pixel row are transferred to the output transfer path 70during a first horizontal blanking period following the first verticalblanking period. These signal charges are sequentially output from theoutput unit 80 during a first effective signal period following thefirst horizontal blanking period (image signal output process).

The signal charges read from the photoelectric conversion elements 22 ofthe second pixel row are transferred to the output transfer path 70during a second horizontal blanking period following the first effectivesignal period. These signal charges are sequentially output from theoutput unit 80 during a second effective signal period following thesecond horizontal blanking period (image signal output process).

The signal charges read to the vertical transfer CCDs 30 are processedin a manner similar to the process used for a usual interlace driveoperation. A field image signal thinned by a quarter or a frame imagesignal thinned by a quarter can thus be obtained.

Similar to the thinning operation described above, the quarter thinningoperation may be performed by using optional two pixel rows. A pixel rowused for the quarter thinning operation can be selected as desired. Inaccordance with the pixel rows used for the quarter thinning operation,a specification of interconnection is determined between the pulsesupply terminals 85 a, 85 b, 85 c ₁, 85 c ₂, 85 d ₁, and 85 d ₂ and thetransfer electrodes 32 and 33 and transfer electrodes 61, 62 , 63, 64,and 65. If IT-CCD 120 is modified to a color IT-CCD, a pixel row usedfor the thinning operation is determined while the layout of colorfilters of the color filter array is taken into consideration.

The above thinning operation is not to read signal charges of all pixelsbut to obtain image signals always thinned to a quarter of the totalnumber of pixel rows. IT-CCD 120 shown in FIG. 12 has eight pixel rows.Therefore, only two read operations in the horizontal direction areperformed for the quarter thinning operation. IT-CCD in practical usehas the number of pixel rows, e.g., 600 pixel rows or more.

If the photosensitive area of IT-CCD has a structure of n-stages in thedirection D_(v), each stage has the same structure as that of thephotosensitive area 10 shown in FIG. 12, the thinning operation isperformed from the first stage to the n-th stage to obtain a frame imagesignal thinned to a quarter. In this case, signal charges are read fromthe photoelectric conversion elements 22 of a desired pixel row tocorresponding vertical transfer CCDs at the same time at each stage. Thesignal charges read at each stage are sequentially transferred to theoutput transfer path 70 by each vertical transfer CCD 30, andtransferred in the output transfer path 70 to be sequentially outputfrom the output unit 80.

With the above quarter thinning operation, all color signals necessaryfor obtaining a color image through additive of subtractive colorprocesses can be obtained during one field period. Therefore, the memoryto be used for the coloring signal processes is sufficient if it has acapacity of one or two pixel rows. A field memory and a mechanicalshutter are not essential.

If an optimum setting of exposure conditions (shutter time and iris), afocus adjustment, a monitor image display and the like of a digitalstill camera are to be performed at a time, it is necessary to obtain animage output signal at a high frame frequency of about 30 frames/sec.

For a high resolution digital still camera, it is desired to use IT-CCDhaving one million pixels or more.

If the number of pixels of IT-CCD exceeds one million, it takes aconsiderably long time such as several frames/sec to obtain an imagesignal output of one frame. It is therefore impossible to perform at atime an optimum setting of exposure conditions, a focus adjustment, amonitor image display and the like.

In order to realize a high resolution digital still camera, it isdesired to use IT-CCD capable of performing at a high frame frequencythe operation other than an operation of reading a still image recordedupon depression of a shutter.

IT-CCD 120 can perform a normal interlace drive and a quarter pixel rowthinning drive. The frame frequency of the thinning drive is four timesthat of the normal interlace drive. IT-CCD 120 provides a structuresuitable for obtaining an image signal of a high frame frequency.

Next, IT-CCD according to a fourth embodiment will be described withreference to FIG. 13. FIG. 13 is a schematic plan view of IT-CCD 130 ofthe fourth embodiment.

IT-CCD 130 shown in FIG. 13 has the same structure as that of IT-CCD 100excepting: (i) the shape of a light receiving area of each pixel; (ii)the number of pulse supply terminals for supplying predetermined drivepulses to the transfer electrodes constituting each vertical transferCCD and the transfer electrodes in the adjusting portion; and (iii) aspecification of interconnection between the pulse supply terminals andtransfer electrodes. In FIG. 13, like constituent elements to thoseshown in FIG. 1 and FIG. 12 are represented by using identical referencenumerals used in FIG. 1 and FIG. 12.

As shown in FIG. 13, the shape of the light receiving area 51 a of eachpixel of IT-CCD 130 is a rhombus having a longer diagonal substantiallyparallel to the direction D_(v) and a shorter diagonal substantiallyparallel to the direction D_(H), similar to IT-CCD 120 shown in FIG. 12.

IT-CCD 130 has eight pulse supply terminals 86 a, 86 b, 86 c, 86 d, 86e, 86 f, 86 g and 86 h to supply predetermined drive pulses to thetransfer electrodes 32 and 33 and transfer electrodes 61, 62 and 63.

The pulse supply terminals 86 a, 86 b, 86 c, 86 d, 86 e, 86 f, 86 g and86 h are electrically connected to predetermined transfer electrodesamong those transfer electrodes 32, 33, 61, 62 and 63.

The shapes, sizes and directions of light receiving areas 51 a of pixelsof IT-CCD 130 shown in FIG. 13 are substantially the same. Therefore,from the same reason as that of IT-CCD 100 of the first embodiment,although the pixel-shift layout is employed, adjacent two pixel rows canbe easily prevented from having a difference in the light convergenceefficiency and sensitivity of a pixel.

From the same reason described with IT-CCD 100 of the first embodiment,IT-CCD 130 can easily improve the pixel density without using highlysophisticated ultra fine patterning techniques and can easily suppressan increase in power consumption.

A color IT-CCD can be formed by providing IT-CCD 130 with a color filterarray. The color filter array can be formed, for example, by using aprocess similar to that used for forming the color filter array ofIT-CCD 110 of the second embodiment.

If IT-CCD 130 is modified to a color IT-CCD, from the same reason asthat described with IT-CCD 110 of the first embodiment, color shading isnot likely to occur.

For the interlace drive of IT-CCD 130, predetermined vertical pulsesignals are applied to the pulse supply terminals 86 a, 86 b, 86 c, 86d, 86 e, 86 f, 86 g and 86 h, a horizontal pulse signal Ha is applied tothe pulse supply terminal 88 a, and a horizontal pulse signal Hb isapplied to the pulse supply terminal 88 b. In this manner, one frame canbe divided into eight fields including the first to eighth pixel rows.

An image signal output of each field can be obtained by an operation(refer to IT-CCD 100 of the first embodiment) similar to that used forobtaining an image signal output of each field among four fields dividedfrom one frame for the interlace drive. This operation is executed forthe first to eighth fields to obtain an image output signal of oneframe.

If adjacent two fields along the direction D_(v), e.g., the third andfourth fields, are selected and the above operation is repeated, theimage signal output of the predetermined two fields can always beobtained.

Each vertical transfer CCD 30 of IT-CCD 130 can be eight-phase driven.In an eight-phase drive type CCD, one potential well is formed overconsecutive six to seventh charge transfer stages and signal chargesaccumulated in the potential well can be transferred. In a four-phasedrive type CCD, one potential well is formed over consecutive two tothree charge transfer stages and signal charges accumulated in thepotential well can be transferred.

If the designed patterns of the transfer electrodes 32 and 33 are thesame, the eight-phase drive type CCD can transfer signal charges abouttwo to three times in amount as compared to the four-phase drive typeCCD.

The channel width of the charge transfer channel of each verticaltransfer CCD 30 of IT-CCD 130 can therefore be narrowed so that the areaof the photoelectric conversion element 22 and the light receiving area51 a of each pixel can be made large correspondingly. It is thereforepossible to increase the sensitivity and saturated output and thedynamic range.

A color IT-CCD can be formed by providing IT-CCD 130 with a color filterarray. The color filter array can be formed., for example, by using aprocess similar to that used for forming the color filter array ofIT-CCD 110 of the second embodiment.

A camera requiring a color image signal for each field executes acoloring process for each field image output signal output from theoutput unit 80 to obtain a color image signal of each field.

A camera requiring a color image signal for a frame temporarily storesconsecutive eight field image output signals in a frame memory, andexecutes a coloring signal process for the image output signals of oneframe to obtain a color image signal for each frame. In this case, it ispreferable to use a mechanical shutter in order to prevent the exposedtiming of each field from being shifted. The mechanical shutter isclosed after the end of the first vertical blanking period until thestart of the eighth vertical blanking period so as not to enter anoptical image in pixels. In this manner, the first to eighth field imageoutput signals at the same timing can be obtained. This is applicablealso to a camera requiring a black-white image signal of one frame. Fora camera requiring only one frame image, the mechanical shutter isclosed after the first vertical blanking period. It is thereforepossible to suppress the generation of smear in the first to eighthfield images.

Next, IT-CCD according to a fifth embodiment will be described withreference to FIG. 14. FIG. 14 is a schematic cross sectional viewpartially showing an output transfer path 70 b of IT-CCD 140 of thefifth embodiment.

IT-CCD 140 has the same structure as that of IT-CCD 100 excepting thatthe output transfer path 70 of IT-CCD 100 of the first embodiment isreplaced by the output transfer path 70 b shown in FIG. 14. In FIG. 14,like constituent elements to those of the output transfer path 70 ashown in FIG. 11 are represented by using identical reference numeralsused in FIG. 11, and the description thereof is omitted.

An output transfer path 70 b is composed of a two-phase drive type CCDhaving a three-layer polysilicon electrode structure. Similar to theoutput transfer path 70 a of IT-CCD 110 shown in FIG. 11, the outputtransfer path 70 b has a charge transfer channel 71. The charge transferchannel 71 is formed by alternately forming a predetermined number ofn⁺-type regions 71 a and n-type regions 71 b in predetermined areas of ap-type well 2 formed in the principal surface of a semiconductorsubstrate 1. The n⁺-type region 71 a contains n-type impurities at ahigh concentration, and the n-type region 71 b contains n-typeimpurities at a low concentration. The width of the n⁺-type region 71 ais wider than that of the n-type region 71 b. The charge transferchannel 71 extends along the direction D_(H).

The output transfer path 70 b has predetermined numbers of transferelectrodes 72, 73 and 77 made of polysilicon layers. Each transferelectrode 72 is formed over the n⁺-type region 71 a. Each transferelectrode 73 and each transfer electrode 77 are alternately formed overthe n-type region 71 b.

The transfer electrodes 72, 73 and 77 traverse the charge transferchannel 71. The end portions of the transfer electrode 73 on thetransfer electrode 72 side overlap the transfer electrodes 72. The endportions of the transfer electrode 77 on the transfer electrode 73 sideoverlap the transfer electrodes 73. The transfer electrodes 72, 73 and77 have a so-called overlapping transfer electrode structure.

A potential well region is formed by the n⁺-type region 71 a and thetransfer electrode 72 over the n⁺-type region 71 a. Similarly, apotential barrier region is formed by the n-type region 71 b and thetransfer electrode 73 or 77 formed over the n-type region 71 b. Thecharger transfer stage is formed by one potential barrier region and onepotential well region on the next downstream side (on the side of theoutput unit 80, this definition is also used in the following).

Both the transfer electrode 73 or 77 forming the potential barrierregion and the transfer electrode 72 forming the potential well regionon the next downstream side are applied with a predetermined voltagelevel at the same time to form one charge transfer stage.

Electric insulating films are formed on the transfer electrodes 72, 73and 77. These electric insulating films and above-mentioned electricinsulating film (passivation film) are drawn in FIG. 14 as one electricinsulating film 74 a for the simplicity of drawing.

Two pulse supply terminals are used for supplying predetermined drivepulses to the output transfer path 70 b, similar to the output transferpath 70 shown in FIG. 1. The transfer electrode 72 and the transferelectrode 73 or 77 on the next downstream side are electricallyconnected to the same pulse supply terminal. Adjacent two transferelectrodes 72 with the transfer electrode 73 or 77 being interposedtherebetween are electrically connected to different pulse supplyterminals.

An output transfer path made of a two-phase drive type CCD having athree-layer polysilicon electrode structure has a relatively gentledesign rule as compared to an output transfer path made of a two-phasedrive type CCD having a two-layer polysilicon electrode structure. Forexample, if the two-phase drive type CCD having the two-layerpolysilicon electrode structure is made to have the so-calledoverlapping transfer electrode structure shown in FIG. 7 or 11, it isnecessary to set the gap between transfer electrodes 73 approximatelyequal to or smaller than the gap between transfer electrodes 72. Formingsuch transfer electrodes 73 is severe from the viewpoint of a designrule.

In the two-phase drive type CCD 70 b having the three-layer polysiliconelectrode structure shown in FIG. 14, forming the transfer electrodes 73is not severe.

IT-CCD having a fine pixel pitch (pitch P₂ of photoelectric conversionelements) along the photoelectric conversion element row direction(direction D_(H)) can therefore be formed by using the output transferpath being composed of a two-phase drive type CCD having the three-layerpolysilicon electrode structure. Electrodes made of material other thanpolysilicon may also be used for forming such IT-CCD.

IT-CCDs of the embodiments have been described. The invention is notlimited only to the embodiments.

IT-CCDs of the embodiments have photoelectric conversion elements(photodiodes), vertical transfer CCDs, an output transfer path and thelike formed on an n-type semiconductor substrate with a p-type well.Photoelectric conversion elements (photodiodes), vertical transfer CCDs,an output transfer path and the like of IT-CCD may be formed on a p-typesemiconductor substrate. Photoelectric conversion elements(photodiodes), vertical transfer CCDs, an output transfer path and thelike of IT-CCD may be formed in a semiconductor layer formed on asapphire substrate or the like. In this specification, a term“semiconductor substrate” is intended to include a substrate made ofmaterial different from semiconductor and formed with a semiconductorlayer for forming photoelectric conversion elements (photodiodes),vertical transfer CCDs, an output transfer path and the like in thesemiconductor layer.

The shape in plan view of a photoelectric conversion element may be arectangle (including a rhombus), a polygon having five sides or morewith all internal angles having an obtuse angle, a polygon having fivesides or more with obtuse and acute internal angles, a shape havingrounded corners of such shapes, or the like.

The shape in plan view of the photoelectric conversion element regiondefined by two adjacent transfer electrodes is not limited only to ahexagon, but other shapes may also be used such as a rectangle(including a rhombus), a pentagon, a polygon having seven sides or more,and a shape having rounded corners of such shapes.

The number of charge transfer stages per one photoelectric conversionelement in the vertical transfer CCD is not limited only to two, butother numbers three and four may be used.

The shape in plan view of each section of the charge transfer channel inthe vertical transfer CCD may be a curved line or a line formed by astraight line and a curved line, in addition to a straight line.

The shape of each transfer electrode in the vertical transfer CCD ispreferably a shape connecting the connection area and transfer pathforming area at an obtuse angle or a shape smoothly connecting theconnection area and transfer path forming area.

Adjacent two transfer electrodes of the vertical transfer CCD may bemade of different materials. The material of the transfer electrode maybe metal such as aluminum, tungsten and molybdenum, or alloy of two ormore of such metals, in addition to polysilicon.

The connection areas of adjacent two transfer electrodes may besuperposed completely as shown in FIG. 6A, overlapped in the sideportion of one of the connection areas, or positioned side by side.

The shape of the light receiving area of each pixel may be a rectangle(including a rhombus), a polygon having five sides or more with allinternal angles having an obtuse angle, a polygon having five sides ormore with obtuse and acute internal angles, a shape having roundedcorners of such shapes, or the like. In order to eliminate a differencein the light convergence efficiency and sensitivity between pixels ofadjacent two pixel rows, the shape of the photosensitive area of eachpixel is preferably line symmetrical with both the directions D_(v) andD_(H).

It is not necessarily required that the readout gate electrode structurecovers in plan view the whole readout gate region. The readout gateregion may extend in plan view from the readout gate structure towardthe photoelectric conversion element side.

The method of driving the vertical transfer CCD is not limited only tothe drive method described above, but other methods may also be used inaccordance with the application field of IT-CCD or the like. Inaccordance with the selected drive method, the number of pulse supplyterminals for supplying predetermined pulses to transfer electrodes andthe specification of interconnection between the pulse supply terminalsand transfer electrodes may be changed. The method of driving the outputtransfer path may also be changed.

If the two-phase drive type CCD is used as the output transfer path,adjacent transfer electrodes of the two-phase drive type CCD may be madeof different materials. The material of the transfer electrode may bemetal such as aluminum, tungsten and molybdenum, or alloy of two or moreof such metals, in addition to polysilicon.

The number of charge transfer stages of the adjusting portion per onevertical transfer CCD is preferably determined so as to satisfy thefollowing condition: if the charge transfer stages and vertical transferCCD are driven under the same condition, the potential barrier is formedin the most downstream charger transfer stage immediately before signalcharges are transferred to the output transfer path. If this conditionis satisfied, it becomes easy to prevent charges to be transferred fromthe adjusting portion to the output transfer path from flowing away fromthe adjusting charge transfer channel.

The shape in plan view of a micro lens formed on the light receivingarea and covering in plan view the light receiving area may be arectangle, a rectangle with rounded corners, a polygon having five sidesor more with all internal angles having an obtuse angle, a circle, anellipsoid or the like. The shape in plan view of the micro lens can bedetermined in accordance with the shape of the light receiving area ofeach pixel. A micro lens structure having a plurality of condenserlenses including at least one inner lens may be formed on the lightreceiving area of each pixel.

A pitch between micro lenses in the direction D_(v) may be the same asor slightly different from the pitch P₁ between photoelectric conversionelements in the direction D_(v). If the pitch between micro lenses inthe direction D_(v) is set different from the pitch P₁, the position ofeach micro lens is changed from the following viewpoints.

The position of each micro lens is changed so that the focal position isat a desired position in the light receiving area of the pixel, forexample, at a position where the highest sensitivity and resolution areobtained. This position is changed in accordance with an incidence lightdirection different at each position in the photosensitive area. Inorder to improve the pixel sensitivity and resolution, it is preferablethat the photoelectric conversion region covers an area near the focalposition of the micro lens as broad as possible.

From the same reason, a pitch between micro lenses in the directionD_(H) may be the same as or slightly different from the pitch P₂ betweenphotoelectric conversion elements in the direction D_(H).

When the positional relation between a photoelectric conversion elementand a micro lens is substantially the same for all pixels, the positionof an image point formed by a micro lens on the photoelectric conversionelement is slightly different in the central area, upper area and lowerarea of the photoelectric conversion element column. In order tosuppress a shift of the position of an image point formed by a microlens on the photoelectric conversion element from a desired position, itis preferable to change the position of each micro lens by the followingthree methods (1) to (3). (1) As schematically shown in FIG. 15A, thepositions of micro lenses 93 in the upper and lower areas of eachphotoelectric conversion element column 20 are changed more to thecentral area as the position of the photoelectric conversion elementbecomes remoter from the central area. Arrows in FIG. 15A indicate theposition change directions of the micro lenses 93. (2) As schematicallyshown in FIG. 15B, the positions of micro lenses 93 in right and leftareas of each photoelectric conversion element row 21 are changed moreto the central area of the photosensitive area 10 along the directionD_(H) as the position of the photoelectric conversion element becomesremoter from the central area. Arrows in FIG. 15B indicate the positionchange directions of the micro lenses 93. (3) As schematically shown inFIG. 15C, the positions of micro lenses 93 are changed more to thecentral area of the photosensitive area 10 along the directions D_(H)and D_(v) as the position of the photoelectric conversion elementbecomes remoter from the central area. Arrows in FIG. 15C indicate theposition change directions of the micro lenses 93.

By changing the positions of the micro lenses by the methods (1) to (3),luminance shading can be improved.

The color filter array of IT-CCD may use various color filters capableof taking a color image. A color filter array of three primary colors(red, green and blue) and a color filter array of complementary colorsare known.

A complementary color filter array may be composed of: (i) color filtersof green (G), cyan (Cy) and yellow (Ye); (ii) color filters of cyan(Cy), yellow (Ye) and white or achromatic (W); (iii) color filters ofcyan (Cy), magenta (Mg), yellow (Ye) and green (G): (iv) color filtersof cyan (Cy), yellow (Ye), green (G), and white or achromatic (W); orthe like.

FIG. 16A is a plan view showing an example of a complementary colorfilter array 91 a having the color filters (i). FIG. 16B is a plan viewshowing an example of a complementary color filter array 91 b having thecolor filters (ii). FIG. 16C is a plan view showing an example of acomplementary color filter array 91 c having the color filters (iii).FIG. 16D is a plan view showing another example of the complementarycolor filter array 91 c having the color filters (iii). FIG. 16E is aplan view showing an example of a complementary color filter array 91 dhaving the color filters (iv).

In FIGS. 16A to 16E, hexagons surrounding alphabet G, Cy, Ye, W and Mgshow color filters. The alphabet G, Cy, Ye, W and Mg shows the colors ofcolor filters. Vertical transfer CCDs 30 are also drawn in FIGS. 16A to16E.

The layout of color filters of a three primary color filter array is notlimited only to that shown in FIG. 10. Similarly, the layouts of colorfilters of complementary color filter arrays are not limited only tothose shown in FIGS. 16A to 16E.

IT-CCD of each embodiment has photoelectric conversion elements(photodiodes) 22 formed in the p-type well 2 of the n-type semiconductorsubstrate 1. A vertical type overflow drain structure can therefore beformed in IT-CCD of the embodiment. An electronic shutter can thereforebe formed. In forming the vertical type overflow drain structure inIT-CCD, a reverse bias is applied between the p-type well 2 and thelower region (region lower than the p-type well 2) of the n-typesemiconductor substrate 1. A horizontal type overflow drain structuremay be formed in place of a vertical type overflow drain structure. Avertical or horizontal type overflow drain structure facilitates tosuppress blooming.

Various IT-CCD driving methods may be selectively used. In accordancewith the selected method, the structure of the driving pulse supplymeans for supplying predetermined drive pulses to the vertical transferCCDs (transfer electrodes constituting the vertical transfer CCDs) andoutput transfer path (transfer electrodes constituting the outputtransfer path) may be changed.

It is apparent that other various modifications, improvements,combinations, and the like can be made by those skilled in the art.

IT-CCD of the invention can form relatively wide transfer electrodes ofthe output transfer path (horizontal transfer CCD) even if a pixeldensity is increased. According to the invention, IT-CCD with low costcan be provided which has a high pixel density and small powerconsumption.

We claim:
 1. A solid state image pickup device, comprising: asemiconductor substrate; a number of photoelectric conversion elementsdisposed on a surface of the semiconductor substrate in a plurality ofcolumns and rows, a photoelectric conversion element column and aphotoelectric conversion element row each being composed of a pluralityof photoelectric conversion elements, a plurality of photoelectricconversion elements of an even column being shifted in a columndirection by about a half of the pitch between adjacent photoelectricconversion elements in each photoelectric conversion element column,from a plurality of photoelectric conversion elements of an odd column,and a plurality of photoelectric conversion elements of an even rowbeing shifted in a row direction by about a half of the pitch betweenadjacent photoelectric conversion elements in each photoelectricconversion element row, from a plurality of photoelectric conversionelements of an odd row; charge transfer channels each provided for twophotoelectric conversion element columns and formed in the surface ofthe semiconductor substrate in an area in plan view between the twophotoelectric conversion element columns, said charge transfer channelextending as a whole along a direction of the photoelectric conversionelement column and having a zigzag shape; a plurality of transferelectrodes formed on the semiconductor substrate, traversing in planview each of said charge transfer channels, said transfer electrodehaving transfer path forming areas same in number as said chargetransfer channels, the transfer path forming area forming one chargetransfer stage in a cross area in plan view with a corresponding chargetransfer channel, adjacent two transfer electrodes with onephotoelectric conversion element row being interposed therebetweenrepeating in plan view divergence and convergence and surrounding inplan view each photoelectric conversion element in the photoelectricconversion element row of an even or odd row to define photoelectricconversion element region, said transfer electrode extending as a wholealong a direction of the photoelectric conversion element row; a readoutgate region provided for each photoelectric conversion element in thesurface of the semiconductor substrate to be contiguous to thephotoelectric conversion element and to a corresponding charge transferchannel, said readout gate region corresponding to the photoelectricconversion element of the even row and said readout gate regioncorresponding to the photoelectric conversion element of the odd rowbeing covered in plan view with different transfer electrodes; and anadjusting portion formed downstream of downstream ends of said chargetransfer channels, said adjusting portion including a plurality ofcharge transfer stages for adjusting a phase of signal chargestransferred from each of said charge transfer channels.
 2. A solid stateimage pickup device according to claim 1, wherein said plurality oftransfer electrodes include a plurality of first and second transfergates formed alternately, the transfer path forming area of one of thefirst and second transfer electrodes being formed on each readout gateregion contiguous to a corresponding photoelectric conversion element ofthe odd row, and the transfer path forming area of the other of thefirst and second transfer electrodes being formed on each readout gateregion contiguous to a corresponding photoelectric conversion element ofthe even row.
 3. A solid state image pickup device according to claim 1,wherein a width of the transfer path forming area of each of the firstand second transfer electrodes is wider than a width of the other areathereof.
 4. A solid state image pickup device according to claim 1,wherein each of said charge transfer channel and said transferelectrodes form two charge transfer stages for each said photoelectricconversion element row.
 5. A solid state image pickup device accordingto claim 1, further comprising a light shielding film formed over thesemiconductor substrate, said light shielding film being formed with anopening on each corresponding photoelectric conversion element.
 6. Asolid state image pickup device according to claim 5, wherein shapes,sizes and directions in plan view of the openings are substantiallysame.
 7. A solid state image pickup device according to claim 5, whereina shape in plan view of the opening is a rectangle, a pentagon, or ahexagon.
 8. A solid state image pickup device according to claim 5,further comprising a micro lens formed on each opening and covering inplan view the opening.
 9. A solid state image pickup device according toclaim 8, further comprising a color filter disposed between each openingand a corresponding micro lens and covering in plan view the opening.10. A solid state image pickup device according to claim 1, furthercomprising a driver circuit for applying a field shift pulse to each ofsaid transfer electrodes covering the readout gate regions.
 11. A solidstate image pickup device according to claim 1, further comprising anoutput transfer path being composed of a two-phase drive type CCD havinga two-layer electrode structure or a two-phase drive type CCD having athree-layer electrode structure, said output transfer path receivingfrom said charge transfer channels the signal charges accumulated insaid photoelectric conversion elements through photoelectric conversionand transferring the received signal charges toward a predetermineddirection.
 12. A solid state image pickup device according to claim 1,wherein said adjusting portion includes charge transfer stages forchanging a transfer direction of the signal charges from a directionslanted from the direction of the photoelectric conversion elementcolumn to the column direction.
 13. A driving method for a solid stateimage pickup device comprising: a semiconductor substrate; a number ofphotoelectric conversion elements disposed on a surface of thesemiconductor substrate in a plurality of columns and rows, aphotoelectric conversion element column and a photoelectric conversionelement row each being composed of a plurality of photoelectricconversion elements, a plurality of photoelectric conversion elements ofan even column being shifted in a column direction by about a half ofthe pitch between adjacent photoelectric conversion elements in eachphotoelectric conversion element column, from a plurality ofphotoelectric conversion elements of an odd column, and a plurality ofphotoelectric conversion elements of an even row being shifted in a rowdirection by about a half of the pitch between adjacent photoelectricconversion elements in each photoelectric conversion element row, from aplurality of photoelectric conversion elements of an odd row; chargetransfer channels each provided for two photoelectric conversion elementcolumns and formed in the surface of the semiconductor substrate in anarea in plan view between the two photoelectric conversion elementcolumns, said charge transfer channel extending as a whole along adirection of the photoelectric conversion element column and having azigzag shape; a plurality of transfer electrodes formed on thesemiconductor substrate, traversing in plan view each of said chargetransfer channels, said transfer electrode having transfer path formingareas same in number as said charge transfer channels, the transfer pathforming area forming one charge transfer stage in a cross area in planview with a corresponding charge transfer channel, adjacent two transferelectrodes with one photoelectric conversion element row beinginterposed therebetween repeating in plan view divergence andconvergence and surrounding in plan view each photoelectric conversionelement in the photoelectric conversion element row of an even or oddrow to define photoelectric conversion element region, said transferelectrode extending as a whole along a direction of the photoelectricconversion element row; a readout gate region provided for eachphotoelectric conversion element in the surface of the semiconductorsubstrate to be contiguous to the photoelectric conversion element andto a corresponding charge transfer channel, said readout gate regioncorresponding to the photoelectric conversion element of the even rowand said readout gate region corresponding to the photoelectricconversion element of the odd row being covered in plan view withdifferent transfer electrodes; and an adjusting portion formeddownstream of downstream ends of said charge transfer channels, saidadjusting portion including a plurality of charge transfer stages foradjusting a phase of signal charges transferred from each of said chargetransfer channels, the driving method comprising the steps of: readingthe signal charges accumulated in each photoelectric conversion elementof at least one photoelectric conversion element row, to the chargetransfer channel corresponding to the photoelectric conversion elementvia the readout gate region contiguous to the photoelectric conversionelement, during one vertical blanking period; and converting the signalcharges read to the charge transfer channel into an image signal andoutputting the image signal, during a period after the one verticalblanking period and before a next vertical blanking period.